Senior STA Engineer

Summary

We are looking for a Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff…

This is a short summary. The full description, and the application form, are on Astera Labs’s own careers page.

Location

Ahmedabad, Gujarat, India

Visa sponsorship

No

Relocation support

No

Salary

Not listed

Role family

Software Engineer (general)

Posted

11 Sept 2026 · 36 days ago

Last checked

17 Oct 2026