DFT Engineer

Summary

Own RTL design for assigned blocks from microarchitecture through synthesis sign-off Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality Partner with architecture to translate…

This is a short summary. The full description, and the application form, are on Astera Labs’s own careers page.

Location

Bengaluru, Karnataka, India

Visa sponsorship

No

Relocation support

No

Salary

$133,200 to $185,000

Role family

Software Engineer (general)

Posted

24 Sept 2026 · 23 days ago

Last checked

17 Oct 2026