Principal Logic Design Engineer - UALink IP/Subsystem

Summary

We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems . Lead architecture and RTL development for UALink IP/subsystems. Translate protocol and system…

This is a short summary. The full description, and the application form, are on Astera Labs’s own careers page.

Location

Bengaluru, Karnataka, India

Visa sponsorship

No

Relocation support

No

Salary

Not listed

Role family

Software Engineer (general)

Posted

17 Sept 2026 · 30 days ago

Last checked

17 Oct 2026