Lead Logic Design - PCIE IP/Subsystem Engineer

Summary

We are seeking a Lead Logic Design Engineer with deep expertise in micro-architecture and RTL design to lead the development of complex IPs/subsystems. The candidate will provide technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up. Lead…

This is a short summary. The full description, and the application form, are on Astera Labs’s own careers page.

Location

Bengaluru, Karnataka, India

Visa sponsorship

No

Relocation support

No

Salary

Not listed

Role family

Software Engineer (general)

Posted

17 Sept 2026 · 30 days ago

Last checked

17 Oct 2026