Lead Logic Design for UALink IP/Subsystem Engineer

Summary

Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design. Lead UALink IP/subsystem RTL development. Translate protocol requirements into detailed microarchitecture. Design high-performance…

This is a short summary. The full description, and the application form, are on Astera Labs’s own careers page.

Location

Bengaluru, Karnataka, India

Visa sponsorship

No

Relocation support

No

Salary

Not listed

Role family

Software Engineer (general)

Posted

10 Sept 2026 · 37 days ago

Last checked

17 Oct 2026